A field programmable gate array (FPGA) utilizes an array of logic blocks, which can be configured by the user. The term “field programmable” implies that the device is programmable outside the factory where it is produced.
The internal architecture of a FPGA device has three main parts, namely:
- The array of logic blocks
- The programmable interconnects
- I/O blocks.
The figure below illustrates the architecture of a typical FPGA.
Each of the I/O blocks provides an individual selectable input, output or bidirectional access to one of the general purpose I/O pins on the FPGA package. The logic blocks in FPGA are just as complex as a couple of logic gates or look-up table feeding a flip-flop. The programmable interconnects connect logic blocks to other logic blocks and also I/O blocks to logic blocks.
FPGAs provide a much higher logic density and much larger performance features compared to complex programmable logic device (CPLD). Some of the modern FPGA devices offer a logic complexity equivalent to that of eight million systems gates. Additionally, these devices offer features such as built-in hard-wired processors, large memory, clock management systems and support for many of the modern device-to-device signalling technologies. FPGAs are extensively used in a variety of applications, which include: data processing and storage, digital signal processing, instrumentation and telecommunication.
FPGAs can be programmed by feeding it with a serial data from a PC after soldering it on the PC board.
Advanced Hardware Resources in FPGAs
Innovation level in FPGA devices puts them on the edge of microelectronics fabrication technology advancements. This has enabled a remarkable amount of resources to be readily available on a single chip. Besides the standard custom logic blocks, hardware resources implemented in FPGAs greatly differ depending on the manufacturer, the architecture/family of devices. The resources that provide most advantages to designers can be classified as follows:
- Integrated functional blocks
- I/O signal conditioning
- Special (radiation-tolerant) blocks
Integrated Functional Blocks
The most normal functional blocks that can be found in current FPGAs are as follows:
Memories
Memories that allow processing speed to be increased, I/O pins to be more efficiently utilized, and the design of the system at the board level to be simplified.
Large amounts of internal memory are available in current FPGAs, in many different arrangements. RAM (single port, simple dual-port, true dual-port and bidirectional dual-port), ROM, or shift registers. From these configurations, it is also possible to implement others such as FIFO or content addressable memories (CAMs). Advantage can also be taken of internal memory blocks to build complex functions, such as arbitrary waveform generators, whose values can be obtained from a table stored in memory.
Arithmetic Circuits
Some devices include a relatively large amount of low-complexity arithmetic blocks. Complex arithmetic blocks (i.e. DSP blocks) are found in advanced FPGAs. Multipliers with non-standard 9, 18, or 36 bit data inputs (available in some devices) allow performance to be enhanced since DSP functions may often not require 16, 24, or 32 bit precision.
Clock Managers
Phase-locked loops (PLLs) and delay-locked loops (DLLs), can be used to compensate clock propagation delays throughout the FPGA, to correct clock duty cycle or phase shifts, or to multiply/divide clock frequency.
Integrated Processors
Embedded processors and peripherals are available in complex FPGA architectures, in order to support system-on-chip (SoC) solutions. Processors include RISC or 8051-based microcontroller cores. Soft processors (that is, processing cores built from standard FPGA resources) are available from Xilinx (PicoBlaze, MicroBlaze) and Altera (Nios, Nios II). The PicoBlaze core is a basic 8 bit microcontroller implemented using a reduced number of logic blocks. The MicroBlaze processor provides a more complex but flexible solution. For example, register bank, instruction, and data sizes can be configured and the user can add custom instructions to the CPU. Peripherals include universal asynchronous receivers/transmitters (UARTs), timers, compare and capture units, multiply-divide units, memory controllers, Ethernet media access controllers, or analog-to-digital converters (ADCs).
I/O Signal Conditioning
Specific resources associated to the I/O pins allow FPGAs to be connected to other devices operating at different voltages, without the requirement for additional interface circuitry and, thus, significantly simplify PCBs and reduce costs. I/O pins are usually grouped in banks, each one of which can be used with a different I/O standard. Some architecture also includes internal terminating resistors, which allow signal integrity hence bandwidth to be improved and ease the design of PCBs.
Special Devices
Radiation-Tolerant FPGAs
FPGAs use in aerospace applications is on upward trend. Antifuse radiation-hardened FPGAs are inherently more radiation-tolerant than SRAM-devices. But, radiation-hardened versions of the latter are also available, providing significant advantages for aerospace applications, because of their higher performance and reconfiguration capabilities, with respect to Antifuse devices.
Non-volatile FPGAs
One-time programmable (OTP) devices are available, providing advantages in some applications, essentially because they do not need auxiliary external resources for configuration at power-on, their switch resistance and capacitance and usually their power consumption are lower, and their noise immunity larger than those of their SRAM-based competitors. Antifuse is the key technology used in non-volatile FPGAs, however, there exist also SRAM-based devices with internal non-volatile configuration memory, in addition to flash-based devices.
Mixed Signal FPGAs
Analog I/O blocks and configurable analog blocks for signal conditioning are available in some devices including analog multiplexers, gate drivers, and analog-to-digital converters (ADCs).
Low Power Devices
FPGAs are usually not power-efficient due to the overhead required to provide configurability. Furthermore, technology scaling down leads to increasing leakage current, hence increasing static power consumption. To overcome these problems, low power FPGAs has been developed. Low power operating modes can be efficiently implemented in Antifuse devices, which, in addition, normally dissipate less dynamic power than SRAM-based ones.
Bottom Line
To sum up, FPGAs provides many advantages and opportunities when hardware reconfiguration capabilities are needed for a given application. While reconfigurable systems are not limited to FPGAs, these are the most significant devices at the commercial level. Although its programmable logic cannot compete with higher performance of other hardware-based solutions like application specific integrated circuits (ASICs), the added flexibility of FPGAs or its lower cost for low volume can be a major decision factor when making a choice between FPGA and other solutions.
Related articles:
- What is a Soft-Core Processor?
- Soft-Core Processor on an ASIC vs. FPGA
- Basic Structure of a Programmable ROM (PROM)
- SIMD, MISD & MIMD Multiple Processor Architectures
- Programmable Array Logic (PAL)
- Programmable Logic Device (PLD)
- Programmable Logic Array (PLA)
