Basic Structure of a Programmable ROM (PROM)

The architecture of a programmable read only memory (PROM) allows the user to use the hardware in implementing an arbitrary combinational function of a given number of inputs. When utilized as a memory device, n inputs of the ROM (called address lines) and m outputs (called data lines) can be used to store 2ⁿm-bit words. When used as a programmable logic device (PLD), it can be used to implement m different combinational functions, with each function being a chosen function of n variables. Any conceivable n-variable Boolean function can be made to appear at any of the m output lines. A typical ROM device with n inputs and m outputs has 2ⁿ hard-wired AND gates at the input and m programmable OR gates at the output. Each AND gate has n inputs, and each OR gate has 2ⁿ inputs. Thus, each OR gate can be used to generate any conceivable Boolean function of n variables, and this generalized ROM can be used to produce m arbitrary n-variable Boolean functions.

The AND array produces all possible minterms of a given number of input variables, and the programmable OR array allows only the desired minterms to appear at their inputs. Figure 1.0 below, shows the internal architecture of a PROM having four input lines, a hard-wired array of 16 AND gates and a programmable array of four OR gates.

A cross (X) indicates an intact or un-programmed fusible link or interconnection and a dot (*) indicates a hard-wired interconnection. PROMs, EPROMs and EEPROMs (Electrically Erasable Programmable Read Only Memory) can be programmed using standard PROM programmers. One of the key limitations of PROMs is their inefficient application of logic capacity. It is not economical to use PROMs for all those applications where only a few minterms are required. Other disadvantages include relatively higher power consumption and an inability to provide safe covers for asynchronous logic transitions. They are typically much slower than the dedicated logic circuits. Moreover, they cannot be applied in implementing sequential logic due to the absence of flip-flops.

You may also read:

• Data Registers
• Choosing Between TTL & CMOS for Your Digital Logic Design
• CPU Registers