Programmable Array Logic (PAL)

Programmable array logic (PAL) architecture has a programmable AND array at the input and a fixed OR array at the output.

The programmable AND array of a PAL device is similar to that of a programmable logic array (PLA) device. In other words, the number of programmable AND gates is usually smaller than the number of required to generate all possible minterms of the given number of input variables.

The OR array is fixed and the AND outputs are equally divided between available OR gates. For example, a practical PAL device may have eight input variables, 64 programmable AND gets and four fixed OR gates, with each OR gate having 16 inputs. That is to say, each OR gate is fed from 16 of the 64 AND outputs.

The figure below shows the internal architecture of a PAL device that has four input lines, an array of eight AND gates at the input and two OR gates at the output:

You may also read:

• Programmable Logic Device (PLD)
• Basic Structure of a Programmable ROM (PROM)
• Data Registers
• Transistor Transistor Logic (TTL)
• CPU Registers

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