Processor architecture can be classified as one of the following four architectures:
- Accumulator-based processor architecture
- Register-based processor architecture
- Stack-based processor architecture
- Pipeline processor architecture
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Accumulator-Based Processor Architecture
In the accumulator-based processor architecture, illustrated above, instructions begin and end in accumulators (Acc A and Acc B), which are specially designated registers. In a typical operation, one of the operands is found in the accumulator and the other is to be fetched from memory. The result of the operation is placed in the accumulator. Since one of the operands needs to be continually fetched from memory, this architecture is slower than the register-based and stack-based architectures. Nonetheless, accumulator-based architecture has the ability to run fairly complicated instructions.
Register-Based Processor Architecture
In register-based processor architecture, both operands are stored in registers and the result of operation is also stored in a register. The registers are typically collocated with the processor. Since the processor and registers operate at the same speed, this architecture is much faster than the accumulator-based architecture. The contents of the register are read from and written to memory using background operation.
Stack-Based Processor Architecture
In a stack-based architecture, both operands and the operation to be performed are stored on the stack, which could be configured around dedicated registers or a special portion of RAM. The result of operation is placed back on the stack.
Pipeline Processor Architecture
In the pipelined architecture, as demonstrated in Figure 1.4 above, there is separate hardware stages of execution of different steps involved in the execution of an instruction. These different steps include fetching an instruction from memory, decoding the instruction, fetching instructions operands from memory or registers, executing the instruction and then finally placing the result back on the memory. Pipelining allows these stages to overlap and perform with parallelism. The overall result is that the execution of an instruction is completed on every clock cycle. Instructions in a pipelined architecture are typically simple instructions that can be implemented within a single stage. These simple instructions act as building blocks for more complex instructions.
You may also read:
- CPU Registers
- RISC vs. CISC Processors
- Digital Computer Hardware Organization
- How Special Function Registers (SFRs) are Mapped into Memory Space
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