Transistor Transistor Logic (TTL)

Transistor transistor logic (TTL) is a logic family implemented with bipolar process technology that combines or integrates NPN transistors, PN junction diodes and diffused resistors in a single monolithic structure to get the desired logic function. The NAND gate is the basic building block of this logic family. We have different subfamilies in this logic family that include: standard TTL, low-power TTL, high-power TTL, low-power Schottky TTL, Schottky TTL, advanced low-power Schottky TTL, advanced Schottky TTL, and fast TTL.

Standard TTL

Figure 1.0 below shows the internal schematic of a standard TTL NAND gate. It is one of the four circuits of 5400/7400, which is quad two input NAND gate.

Transistor Q₁ is a two-emitter NPN transistor, which is equivalent to two NPN transistors with their base and emitter terminals tied together. The two emitters are the two inputs of the NAND gate (Input A and Input B). Diodes D₂ and D₃ are used to limit negative input voltages.

Circuit Operation

The circuit above operates as follows:

When both the inputs are in the logic HIGH state as specified by the TTL family (V_IN = 2 V minimum), the current flows through the base-collector PN junction diode of transistor Q₁, into the base of transistor Q₂. Transistor Q₂ is turned ON to saturation, and as a result, the transistor Q₃ is switched OFF and transistor Q₄ is switched ON. This produces a logic LOW at the output, with V_OL being 0.4 V maximum when it is sinking a current of 16 mA from external loads represented by inputs of logic functions being driven by the output. This is illustrated in the circuit below:

Transistor Q₄ is also referred to as the current-sinking or pull-down transistor owing to its action described above. Diode D₁ is used to prevent transistor Q₃ from conducting even a small amount of current when the output is LOW. When the output is LOW, Q₄ is in saturation and Q₃ will conduct slightly in the absence of D₁. Furthermore, the input current I_IN in the HIGH state is nothing but the reverse-biased junction diode leakage current and is typically 40 μA.

When either of the two inputs or both are in the logic LOW state, the base-emitter region of Q₁ conducts current, driving transistor Q₂ to cut-off in the process. When Q₂ is in the cut-off state, Q₃ is driven to conduction and Q₄ is cut-off. This produces a logic HIGH output with V_OH (min) = 2.4 V guaranteed for minimum supply voltage V_CC and a source current of 400 μA. The current-sourcing action is illustrated in Figure 1.2 below:

Transistor Q₃ is also referred to as the current-sourcing or pull-up transistor due to its action above. Also the LOW level input current I_IL, given by (V_CC-V_BEI)/R₁ is 1.6 mA (max) for maximum V_CC.

Totem-Pole Output Stage

Transistors Q₃ and Q₄ constitute what is referred to as a totem-pole output arrangement. In such arrangement, either Q₃ or Q₄ conducts at a time depending upon the logic status of the inputs. The totem-pole arrangement at the output has certain advantages, the key being; it offers low-output impedance in both the HIGH and LOW output states. In the HIGH state, Q₃ acts as an emitter follower and has an output impedance of about 70 ꭥ. In the LOW state, Q₄ is saturated and the output impedance is approximately 10 ꭥ. Because of the low output impedance, any stray capacitance at the output can be charged or discharged very rapidly through this low impedance, hence allowing quick transitions at the output from one state to the other. One more advantage is that, when the output is in the logic LOW state, transistor Q₄ would require to conduct a fairly large current if its collector were tied to V_CC through R₃ only. A non-conducting Q₃ overcomes this problem. A disadvantage of the totem-pole output configuration results from the switch-off action of Q₄ being slower than the switch-on action of Q₃. Owing to this, there will be a small fraction of time, of the order of a few nanoseconds, when both the transistors are conducting thus drawing heavy current from the supply.

Characteristic Features of standard TTL

To get the information you might need to use regarding the TTL IC devices in your designs, including the internal schematics, pin-out configurations, maximum ratings, operating conditions, and electrical and switching characteristics, check that data sheets from the manufacturer. Just as an example, the characteristics parameters and features of the standard TTL family of devices may include the following:

V_IL = 0.8 V; V_IH = 2V; I_IH = 20 μA; I_IL = 1.6 mA; V_OH = 2.4 V; V_OL = 0.4;  I_OH = 400 μA; I_OL = 16 mA; V_CC = 4.75-5.25 V (74 series) and 4.5 – 5.5 V (54 series); propagation delay (for a load resistance of 400 ꭥ, a load capacitance of 15 pF and an ambient temperature of 25°C) = 22 ns (max) for LOW to HIGH transition at the output and 15 ns (max) for HIGH to LOW output transitions; worst-case noise margin  = 0.4 V; fan-out = 10; 1CCH (for all four gates)= 8 mA; 1_CCL (for all four gates) = 22 mA; operating temperature range  = 0 -70 °C (74-series) and -55 to +125 °C (54-series); speed-power product = 100 pJ; maximum flip-flop toggle frequency = 35 MHz.

Note that, besides the NAND gate which is the fundamental building block of the TTL family, we have other logic gates in the standard TTL family like (NOT Gate or Inverter, NOR Gate, AND Gate, OR Gate, Exclusive-OR Gate, AND-OR-INVERT Gate, Open Collector Gate, Tristate Gate), which in addition to other TTL logic subfamilies will be covered in a future posts.

You may also read:

• 3 Categories of Digital Logic Families
• Flip-Flops in Digital Circuits
• Data Registers
• How to Interface PIC Microcontroller to Input & Output Devices
• Programmable Logic Device (PLD)
• Interfacing LEDs & Electromechanical Relays to Microcontrollers

Related resource: Encyclopedia of Electronic Components for Your Project