Programmable Logic Array (PLA)

A programmable logic array (PLA) device has a programmable AND array at the input and a programmable OR array at the output, which makes it one of the most versatile programmable logic devices.

The figure below, shows the internal architecture of a PLA device with four input lines, a programmable array of eight AND gates at the input and a programmable array of two OR gates at the output.

Programmable Logic Array (PLA) vs. Programmable ROM (PROM)

The number of AND gates in an n-input PROM is always equal to 2ⁿ. In the case of PLA, the number of AND gates in the programmable AND array for n input variables is normally much less than 2ⁿ, and the number of inputs of each of the OR gates equals the number of AND gates. Each OR gate can generate an arbitrary Boolean function with a maximum of minterms equal to the number of AND gates.

A PLA device makes more efficient use of logic capacity than a PROM, but it has its own limitations resulting from two sets of programmable fuses, which makes it relatively more difficult to fabricate, program and test.

Related articles:

• Basic Structure of a Programmable ROM
• Programmable Logic Device (PLD)
• CPU Registers
• Flip-Flops in Digital Circuits