RISC vs. CISC Processors

Both reduced instruction set computer (RISC) and complex instruction set computer (CISC) refer to the instruction set of a microcontroller.

RISC Processors

In an 8-bit RISC microcontroller, data is 8 bits wide but the instruction words are more than 8 bits wide (usually 12, 14, or 16 bits) and the instructions occupy one word in the program memory. Thus the instructions are fetched and executed in one cycle, which improves performance.

RISC processor emphasizes simplicity and efficiency. RISC designs starts with a necessary and sufficient instruction set. The objective of any RISC architecture is to maximize speed by reducing clock cycles per instruction. Almost all computations can be done from a few simple operations. The aim of RISC architecture is to maximize the effective speed of a design by performing infrequent operations in software and frequent functions in hardware, hence obtaining a net performance gain.

To put this concept into perspective, consider any assembly-level language program. It has been observed that it uses the MOV instruction much more often than the MUL instruction. Thus, if the architectural design implements MOV in hardware and MUL in software, there will be a considerable gain in speed, which is the basic feature of RISC technology.

Examples of RISC processors are ARM-based processors, IBM processors, etc.

The main features of a RISC processor are as follows:

• The microprocessor is designed using hard-wired control. For instance, one bit can be dedicated for one instruction. Typically, variable-length instruction formats require microcode design. All RISC instructions have fixed formats, so no microcode is needed.
• The instruction set typically includes only register-to-register load and store.
• The RISC microprocessor executes most of the instructions in a single clock cycle. This is due to the fact that they are implemented in hardware.
• The instructions have a simple format with few addressing modes.
• The RISC microprocessor has several general-purpose registers and large cache memories, which support the very quick access of data.
• The RISC microprocessor processes several instructions simultaneously and so includes pipelining.
• The software can take advantage of more concurrency.

CISC Processors

In a CISC microcontroller, both data and instructions are 8 bits wide. CISC microcontrollers usually have over two hundred instructions. Data and code are on the same bus and cannot be fetched simultaneously.

The primary goal of CISC architecture is to complete a task as few lines of assembly as possible. This is achieved by building processor hardware that is capable of understanding and executing a series of complex operations. In this case, each instruction can execute several low-level instructions. One of the primary advantages of this system is that the compiler has to do very little work to translate a high-level language statement into assembly. Since the length of the code is relatively short, very little RAM is needed to store instructions.

Examples of CISC processors include: Intel, AMD x86 CPUs, among others.

You may also read:

• SIMD, MISD & MIMD Multiple Processor Architectures
• 4 Types of Processor Architectures
• The Pentium Series of Microprocessors
• Basic Architecture of a Microprocessor