The 8085 Microprocessor is one of the most popular microprocessors. In this article we look at some of the basic features and pin-out configuration of this microprocessor.
The block diagram of the 8085 microprocessor is shown below:
The 8085 microprocessor registers include an 8-bit accumulator, an 8-bit flag register (five 1-bit flags, namely sign, zero, auxiliary carry, parity and carry), 8-bit B and C registers (which can be used as one 16-bit BC register pair), 8-bit D and E register (which can be used as one 16-bit DE register pair), 8-bit H and L registers (which can be used as one 16-bit HL register pair), a 16-bit stack pointer and a 16-bit program counter.
8085 microprocessor has four addressing modes. These include register addressing, register indirect addressing, direct addressing mode and immediate addressing mode.
An instruction is a binary pattern designed inside a microprocessor to perform a specific function. The entire group of instructions a microprocessor can perform is referred to as its instruction set. An instruction cycle is defined as the time needed to complete the execution of an instruction. An 8085 instruction cycle consists of 1-6 machine cycles. A machine cycle is defined as the time required completing one operation of accessing memory, I/O and so forth. This will comprise 3-6 T states, which is defined as one subdivision of the operation performed in one clock period.
Figure 1.1 below shows the pin-out configuration of the 8085 microprocessor:
Table 1.0 Pin Details of 8085
| Signals | Descriptions |
| Address bus (12-19, 21-29) | A 16-bit address bus. The lower 8 bits are multiplexed with the data bus. The most significant 8-bits of the memory address (I/O address) address are denoted by A8-A15. The lower 8 bits of the memory address (I/O address) appear on the multiplexed address/data bus (AD0-AD7) for the first clock cycle of the machine cycle. It then becomes the data bus during the second and third clock cycles. |
| Data bus (12-19) | 8-bit data bus is multiplexed with lower 8 bits of the address bus (AD0-AD7) |
| ALE (Address Latch Enable)(30) | It is a positive-going pulse during the first clock state of the machine cycle that indicates that the bits on AD7-AD0 are address bits. It used to latch the low-order address on the on-chip latch from the multiplexed bus. |
| READ (RD) (32) | A LOW on RD indicates that the selected memory or I/O device is ready and the data bus is available for data transfer. |
| WRITE (WR) (31) | A LOW on WR indicates that data on the data bus is to be written into a selected memory or I/O location. Data is set up at the trailing edge of the WR signal. |
| This is a status signal that is used to differentiate between I/O and memory operations. | |
| S1 and S0 (29, 33) | These are status signals and can identify various operations. |
| Vcc (40) Vss | +5 V Ground |
| X1, X2 (20) | A crystal, LC or RC network is connected at these two pins to drive the internal clock generator, X1 can also be external clock input from a logic gate. The frequency is internally divided by 2 to give the internal operating frequency of the processor. The crystal frequency must be at least 1 MHz and must be twice the desired internal clock frequency. |
| CLK OUT – clock output (37) | CLK is twice the X1, X2 input period. |
| INTR: INTerrupt Request (10) | This is a general-purpose interrupt signal. The microprocessor issues an interrupt acknowledge signal (INTA) when the interrupt is requested. |
| RST 7.5 (7) RST 6.5 (8) RST 5.5 (9) | These are restart interrupts. These are vectored interrupts and transfer the program control to specific memory locations. |
| TRAP (6) | It is a non-maskable interrupt and has the highest priority |
| HOLD (39) HLDA (38) | A HOLD signal indicates that another master device is requesting the use of data and address buses. The microprocessor, upon receiving the HOLD request, will relinquish the use of the bus after completion of the current bus transfer. It sends the HOLD ACKNOWLEDGE (HLDA) signal, indicating that it will relinquish the bus in the next clock cycle. |
| READY (35) | A READY signal is used to delay the microprocessor READ or WRITE cycles until a slow responding peripheral is ready to send or accept data. If READY is HIGH during the READ or WRITE cycle, it indicates that the memory or peripheral is ready to send or receive data. If READY is LOW, the processor will wait for an integral number of clock cycles for READY to go to HIGH. |
RESET OUT (3) | A LOW on the RESET IN pin causes the program counter to be set to zero, the buses are tri stated and the microprocessor is reset. RESET OUT indicates that the microprocessor is being reset |
| SID (5) SOD (4) | Serial Input Data. Serial Output Data. |
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