Consider a state where all input/output transfers of data are controlled by the program. When peripherals require attention, they signal the microprocessor by changing the voltage level of an input line. The microprocessor can then respond by jumping to a program service routine for the device. On completion of the routine, a return to the main program occurs. Program control of inputs/outputs is therefore a loop to read inputs and update outputs continuously, with jumps to service routines as needed. This process of repeatedly checking each peripheral device to see if it is ready to send or accept a new byte is referred to as polling.
An option to program control is interrupt control. An interrupt involves a peripheral device activating a separate interrupt request line. The reception of an interrupt results in the microprocessor suspending execution of its main program and jumping to the service routine for the peripheral. The interrupt must not lead to a loss of data and an interrupt handling routine has to be incorporated in the software so that the state of processor registers and the last address accessed in the main program are stored in dedicated locations in memory. Following the interrupt service routine, the contents of the memory are restored and the microprocessor can continue executing the main program from where it was interrupted.
During an interrupt, the following process takes place:
The block diagram below illustrates the Interrupt Control Process:
Unlike a subroutine call, which is located at a specific point in a program, an interrupt can be called from point in the program. The program does not control when an interrupt occurs; the control lies with the interrupting event. For some interrupts it is possible to program the microprocessor to ignore the interrupt request signal unless an enable bit has been set. Such interrupts are referred to as maskable. As an example, with Intel 8051, interrupt sources are individually enabled or disabled through the bit-addressable register IE (interrupt enable) at address 0A8H, a 0 disabling an interrupt and a 1 enabling it. Furthermore, there is a global enable/disable bit in the IE register that is set to enable all external interrupts or cleared to disable all external interrupts.
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