Inter-IC Communication Bus

Inter-IC communication bus (I²C bus) is a serial data bus that was originally developed at Phillips Semiconductors. It is used for communications between integrated circuits (ICs) or modules. The bus allows data and instructions to be exchanged between devices by means of just two wires. This results in a considerable simplification of circuits.

Let’s assume we have a number of device circuits in a number of processes in a plant, one IC each for measuring temperatures and pressures. We would employ I²C common synchronous serial bus to mutually network these ICs.

As mentioned above, the I²C bus has two lines that carry its signals – one line is for clock (SCI) and one is for bidirectional data (SDA) as illustrated in the figure below:

Fig: Inter-IC Communication Bus (I²C Bus)

Both lines are connected to the positive power supply via pull-up resistors, this is done so to ensure that both lines are at a HIGH level when the bus is free and ensure that the signals are pulled up from a LOW to a HIGH level within the required rise time, hence taking account of the bus capacitance. The bus capacitance is the total capacitance of wire, connections and pins. The bus capacitance limits the maximum value of the pull-up resistance due to the specified rise time. The supply voltage limits the minimum value of the pull-up resistance due to the specified minimum sink current of 3 mA for standard mode.

Masters can operate as master transmitters or master receivers. Each device connected to the bus is software addressable by a unique address. The master can address 127 other slaves at an instance. It has a processing element functioning as a bus controller or a microcontroller with I²C bus interface circuit. Each slave can optionally have an I²C bus controller and processing element. A number of masters can also connect to the bus. However, at any instance, there can be only one master, which is one that initiates a data transfer on SDA (serial data) line and which transmits the SCL (serial clock) pulses.

From the master or slave, a data frame has fields beginning from start bit as per table below:

Table 1

Field & Its Length	Description
First field of 1-bit	It is start bit similar to the one in a UART.
Second field of 7 bits	It is referred to as the address field. It defines the slave address being sent the data frame (of many bytes) by the master.
Third field of 1 control bit	It defines whether a read or write cycle is in progress.
Fourth field of 1 control bit	Next bit defines whether present data is an acknowledgement (from the slave).
Fifth field of 8 bits	It is used for IC device data bits.
Sixth field of 1-bit	It is negative acknowledgement bit (NACK) from the master. If active, then acknowledgement after a transfer is not needed from the slave, else acknowledgement is expected from the slave.
Seventh field of 1-bit	It is a stop bit like in a UART.

The following protocol is used:

The master initiates start of data transfer by establishing a HIGH to LOW transition on the serial data line SDA while the serial clock line SCL remains HIGH. This procedure indicates that an address/data stream will follow.
All transactions begin with a START and are terminated by a STOP. A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. A STOP condition is defined by a LOW to HIGH transition on the SDA line while SCL is HIGH.
Data is sent over the SDA line in sequences of nine clock pulses as 8 bits of data followed by an acknowledge bit. Data is transferred with the most significant bit first. The acknowledge bit allows the receiver to signal to the transmitter that the byte is successful received and another byte may be sent.
With data transfers, after the START condition, a slave address is sent. This is 7 bits long followed by an eighth bit which is a data direction bit: a 0 indicates a transmission, that is, WRITE; a 1 indicate a request for data, that is, READ. A data transfer is always terminated by a STOP condition generated by the master. If the master still wishes to communicate it can generate a repeated START condition and message.
The slave device whose address corresponds to the transmitted address responds by pulling the data line LOW during the low period before the ninth clock pulse, this giving an acknowledgement. All other devices on the bus now remain idle while the selected device waits for data to be read from the master or written to the master by the slave.
When all the data bytes have been read or written, stop conditions are determined. In the write mode, the master will pull the data line HIGH during the 10^th clock pulse to indicate stop. In the read mode, the master will pull the data line HIGH during the low period before the ninth clock pulse, and then take the data line LOW during the low period before the 10^th clock pulse, then HIGH during the 10^th clock pulse.
If two or more masters try to put information on the bus, the first to produce a 1 when the other produces a 0 loses out.

An example of I²C compatible IC is the Microchip TC74 (a temperature sensor).

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John Mulindi

John Mulindi has a background in a technical field and he writes on topics ranging from automation, computer systems, embedded systems, mechatronics to measurement and control.