How Special Function Registers (SFRs) are Mapped into Memory Space

There are two basic primary architectures used for mapping special function registers into memory space. In the first type of arrangement, I/O space and memory space are separated as illustrated in Figure 1.0. The I/O devices have a separate address space, which is accomplished by either an extra I/O pin on the CPU physical interface or through a dedicated I/O bus. Thus, access to I/O control registers requires special instructions. It is particularly useful in CPUs having a limited addressing capability. This is generally found in Intel Microprocessors.

In the second arrangement, referred to as memory-mapped I/O, I/O control registers are mapped into memory address space as shown in Figure 1.1 below. Read and write operations to the control registers are done via absolute memory addresses, which could be variables at absolute addresses or pointers to absolute addresses in high-level languages. In this case, no special instructions are required to access I/O control registers. The memory-mapped I/O uses the same bus to address both memory and I/O devices. CPU instructions used to read from or write to memory are also used in accessing I/O devices.

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